1. Technical Field of the Invention
The present invention relates to apparatus and method for testing electronic components, and more particularly to apparatus and method for testing high speed components by test apparatus which reduces power dissipation in the electronic component during testing.
2. Prior Art
In the prior art there are many techniques for testing high speed electronic components. The following are examples of such prior art techniques.
U.S. Pat. No. 5,394,403 entitled "Fully Testable Chip Having Self-Timed Memory Arrays" teaches a system in which system debug operations are facilitated by a test mechanism which includes a timing generator circuit which receives an external clock pulse and provides the self-timed clock pulse to a memory array. To prevent unplanned array modification operations from occurring during a shift mode because a bit shifted into a right enable or clear register at the time a clock pulse derived from the timing circuit is generated, a logic means is provided to disable all clock pulses during the shift mode. A separate shift clock pulse is provided during shift mode to shift the test information into control address and data registers.
Although the patent generally refers to disabling a system clock in a self-test mode, the patent does not teach nor suggest the invention as taught and claimed herein specifically with respect to the solving of power dissipation problems during testing of an integrated circuit chip outside its normal operating environment.
U.S. Pat. No. 5,396,170 shows an integrated test architecture which can be used in conformity with the IEEE 1149.1 test standard (JTAG) and configured on a single chip. The architecture of the patent uses the JTAG standard with additional logic on the single chip which permits "at speed" functional test of integrated circuits.
Although the patent discusses tester architecture for testing an integrated circuit "at speed," the patent does not teach nor suggest the present invention as claimed herein with respect to reduction of power dissipation during testing an integrated circuit out of its operating environment.
U.S. Pat. No. 5,381,420 teaches an interface to internal scan paths within an integrated circuit for synchronizing a test clock and a system clock without adversely affecting the operation of either. The system clock drives the test data through the scan path at the system clock rate, the two clocks are decoupled in that they run independently, being synchronized by the interface for clocking the test data into, through, and out of the scan path.
As above, the 420 patent shows an enhancement to the IEEE 1149.1 standard including a decoupled scan path interface. However, the patent does not teach nor suggest the invention as claimed herein.
U.S. Pat. No. 5,329,533 shows a partial scan built-in self-test technique. However, the patent does not teach nor suggest testing with reduced power dissipation and does not teach nor suggest the present invention as claimed herein.
U.S. Pat. No. 5,254,942 is the parent of U.S. Pat. No. 5,396,170 above and contains the same disclosure as the 170 patent. The comments made with respect to the 170 patent apply to the 942 patent as well.
U.S. Pat. No. 5,208,838 teaches a clock multiplier circuit which is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal depending upon the state of a test mode input signal. By providing the circuitry on an integrated circuit chip, the chip can be driven at its normal operating frequency using lower frequency test equipment.
Although the patent teaches a selectable multiplier circuit for multiplying a test clock signal to a normal operating frequency signal for a device under test, the patent does not teach nor suggest the present invention as claimed herein.
U.S. Pat. No. 5,181,191 teaches a circuit for transferring data between automatic test equipment and an integrated circuit under test pursuant to a slow clock which can have an arbitrarily long period and for operating storage elements in the integrated circuit pursuant to a fast clock having a short period that corresponds to the clock rate at which combinatorial networks in the integrated circuit are to be tested. Although the patent teaches a first clock having a long period and a second clock having a relatively short period, the patent does not teach nor suggest how the clocks are generated.
The patent does not teach nor suggest the present invention as claimed herein.
U.S. Pat. No. 5,095,262 teaches a high speed electro optic test system for testing high speed electronic devices and integrated circuits using a programmable reference clock source providing clock pulses for accurately timing a stimulus pattern in precise synchronism with optical sampling pulses. Although the patent teaches the testing of high speed electronic devices, the use of the optical sampling pulses in synchronism with a stimulus pattern is not related to the present invention as claimed herein.
U.S. Pat. No. 4,969,148 teaches a serial testing technique for embedded memories including a finite state machine adapted to actuate multiplexor units to connect first bits and for each address output a series of test bits shifting those bits through the addressed word by a series of read and write operations and examining those bits after passage through the address word for defects in the memory circuit at that address. Although the patent teaches a finite state machine for controlling application of signals in a serial testing technique or in embedded memory, the patent does not teach nor suggest the present invention as claimed herein.
U.S. Pat. No. 5,355,369 teaches the testing of high speed core logic circuitry by transferring a test program to a special test data register which downloads the program to the logic circuitry under test and uploads the results. This technique allows the core logic to perform the test at its normal operating speed while still retaining compatibility with the JTAG standard for other tests.
The patent does not teach any special relationship between a test apparatus clock and a system clock. Also, the patent requires a dual ported random access memory and a read-only memory for conducting the tests described in the patent. For these reasons, the patent does not teach nor suggest the present invention as claimed herein.
An article in the IBM Technical Disclosure Bulletin, Vol. 33, No. 2, July 1990, at p. 2 and following, describes a logic circuit referred to as COP (common on-chip processor). The COP provides support and control logic needed to achieve built-in self-tests, power on reset, debug, and field support operations at the chip, card, and system levels.
However, there is no intent in the article to perform any power management function. Clock gating is implemented only for the purpose of debugging the chip. The article neither teaches nor suggests the invention as taught and claimed herein as regards reducing power dissipation in a chip during testing outside its operating environment.
An article in the IBM Technical Disclosure Bulletin, Vol. 34, No. 11, April 1992, at p. 115 and following, entitled "Inhibiting Large Current Draw on CMOS Chips During LSSD Scan," attacks the problem of power dissipation during testing of CMOS chips by preventing propagation of data scanned through a scan path to the logic of the chip. During a scan, the latches of a scan path are inhibited from allowing changing data to pass out of the latch, thus reducing the amount of switching and thus reducing power requirements.
Although the article generally relates to reduction of power dissipation during testing, the article does not teach nor suggest the present invention as taught and claimed herein.